Embodiments of the inventive concept relate to stacked semiconductor devices and, more particularly, to stacked semiconductor devices capable of selecting between multiple, stacked chips.
The development of multifunctional, physically smaller electronic devices has motivated the development and design of highly integrated, multifunctional semiconductor devices. To facilitate high integration density and the multi-functionality of contemporary semiconductor devices, so-called “multi-chip packaging” (MCP) techniques have developed. MCP essentially allows a plurality of chips to be assembled and packaged into a single semiconductor device. MCP semiconductor devices may be divided into single-layer and multi-layered devices. Single-layer MCP semiconductor devices configure their constituent plurality of chips in a two dimensional (X and Y directions) arrangement. Multi-stage MCP semiconductor devices, also referred to as “stacked semiconductor devices” configured a plurality of chips in a three dimensional (X, Y and Z directions) arrangement. Within this description, the Z direction may be arbitrarily identified with a vertical stacking of the plurality of chips.
Certain conventional stacked semiconductor devices are configured to receive/provide input/output signals using interconnecting input/output (I/O) terminals. Wire bonding internal to the MCP may be used to connect I/O terminals of the plurality of stacked chips. Alternately, the I/O terminals for the plurality of chips may be connected using wire-bonding external to the MCP. However, the use of the wire-bonding increases inductance, so that the semiconductor device suffers from a decrease in performance an increase in size, and an increase in power consumption.
To make up for the above-described shortcomings, a wafer-level processed stack package (WSP) technique has been developed. In the WSP technique, circuits of the plurality of stacked chips are directly connected through via holes vertically penetrating each chip on a wafer level. These via holes may be formed using a laser, and may subsequently be filled with conductive material(s) to form so-called “through-silicon vias (TSVs)”. Thus, since the stacked semiconductor devices using the WSP technique are configured to directly inter-connect the plurality of chips without the need for wires, it is possible to enhance the performance of the stacked semiconductor device. The vertical distance between the chips can also be reduced, so that it is possible to remarkably reduce the thickness of the stacked semiconductor device. In addition, it is possible to reduce a (X-Y) mounting area required for disposition of the stacked semiconductor device on a board or substrate. That is, the stacked semiconductor devices enjoy greatly enhanced integration density and improved performance with reduced power consumption.
However, since the plurality of chips forming a stacked semiconductor device are so-closely stacked and tightly inter-connected, it is very difficult to directly connect any given chip in the stacked plurality of chips to an external apparatus. Therefore, it is not easy to externally select a particular chip from the stacked plurality of chips. Thus, a method of more readily enabling the selection of each chip in a stacked plurality of chips is needed.